1. Field of the Invention
The present invention relates generally to semiconductor manufacturing. In particular, the invention relates to a method for forming an integrated self-aligned via/contact and interconnect.
2. Description of Related Art
During the process of semiconductor fabrication, alternating layers of a nonconducting material (dielectric), such as silicon dioxide, and of a conductor, such as aluminum tungsten, are formed over the semiconductor substrate. Devices, such as transistors or diodes, among others, are formed at and within the semiconductor substrate. Contact between the lowest layer of conductive material and a region of a device, at and within the semiconductor device (e.g., a source or drain) is made through an opening in a first dielectric layer. The opening is then filled with a conductive material to form a contact that couples the region of the device to the lowest conductive layer. In addition, a vertical opening, known as a via, is filled with conductive material to connect circuits on various layers of a device to one another and to the semiconductor substrate. This conductive material is known as an interconnect.
Openings (i.e., vias and contacts) are often formed using a mask and photolithography. For example, a photosensitive film, such as photoresist, is applied to a surface of the semiconductor substrate. A mask with a desired pattern is used during photolithography to help transfer the desired pattern onto the substrate or a surface on the substrate. The photoresist is then exposed to light through the mask and then developed. The exposed surface of the substrate and photoresist are removed so that the desired pattern is now on the substrate's surface.
Referring to FIG. 1A, a first mask (not shown) patterns an opening in dielectric 103 to form the opening for contact 102 shown in FIG. 1B. A conductive layer is then formed over dielectric 103. Any excess conductive material is removed. The result is shown in FIG. 1B, a contact 102, made of the conductive material, is formed in dielectric 103 on a semiconductor substrate 100. Another conductive layer 105 and then a photosensitive layer are deposited. The photosensitive layer 107 is then patterned to form a metal line as illustrated in FIG. 1C. During the process of etching the conductive layer 105 forms the metal line 106 and an overetch of contact 102 occurs. Consequently, part of contact 102 is etched away as shown in FIG. 1D. This causes reliability problems and possibly circuit failure. The smaller contact area also increases contact resistance and degrades circuit performance. In order to avoid this problem, which is usually caused by forming the contact opening and metal line in two steps, extra chip space is used for overlay alignment errors. Thus, photoresist layer would be extended as shown by the dotted lines 109 to cover contact 102 with some extra space in case of overetching. In turn, the metal line is then etched at dotted lines 111 to prevent overetching of contact 102. Thus, extra chip space must be reserved for overlay alignment errors that could have been used for additional devices. This results in decreased chip density.
Because the size of the contact 102 opening and the overlaying interconnect opening are so small (e.g., 0.18-0.2 micron), it is very difficult to align the two openings accurately using the current photolithography tool set. For example, if contact 102 had a horizontal width of 0.1 micron, a space of about 0.025 micron (in the best case) must be saved on the chip around each side of contact 102, and on mask 104, which patterns the subsequent metal line. This extra space (109, 111) around contact 102 allows room for overlay alignment errors between the contact 102 and the metal line 106. Thus, even assuming a best case scenario, the space around contact 102 increased by 50%, since 0.025.times.2=0.05. This reduces the chip density and results in a larger chip size. Because the semiconductor industry wants increased chip density (e.,g., 100 million or more components on a chip), this is an undesirable effect.
The current lithography tool set is unable to form a via/contact with a subsequently formed interconnect when the via/contact or interconnect has a horizontal width of 0.1 micron or less. E-beam exposure systems and X-Ray systems are two other options for forming openings with a width of 0.1 micron or less. Unfortunately, E-beam and X-ray systems are not feasible for manufacturing use and are still in the research stage. In addition, the cost of using the E-beam and X-ray systems is prohibitive. Thus, what is needed is a manufacturable method for forming very small openings (e.g., sub-0.1 micron) that is not dependent on the current lithography tool set. Furthermore, what is needed is a method that forms an integrated structure that comprises a self-aligned via/contact and interconnect. Because the via/contact and interconnect are self-aligned, no chip space is lost due to overlay alignment errors.